ZHCSG60A 数据表 | 德州仪器 TI.com.cn

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Supply voltage range	AVDD19	–0.3	2.1	V
	AVDD	–0.3	1.4
	DVDD	–0.3	1.4
Voltage applied to input pins	INAP, INAM and INBP, INBM	–0.3	AVDD19 + 0.3	V
	CLKINP, CLKINM	–0.3	AVDD + 0.6
	SYSREFP, SYSREFM, SYNCBP, SYNCBM	–0.3	AVDD + 0.6
	SCLK, SEN, SDIN, RESET, PDN, GPIO1, GPIO2, GPIO3, GPIO4	–0.2	AVDD19 + 0.2
Voltage applied to output pins		–0.3	2.2	V
Temperature	Operating free-air, T_A	–40	85	°C
Temperature	Storage, T_stg	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±1000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
Supply voltage⁽²⁾	AVDD19	1.8	1.9	2.0	V
	AVDD	1.1	1.15	1.25
	DVDD	1.1	1.15	1.2
Temperature	Operating free-air, T_A	–40		85	°C
Temperature	Operating junction, T_J		105⁽¹⁾	125	°C

(1) Prolonged use above this junction temperature may increase the device failure-in-time (FIT) rate.

(2) Always power up the DVDD supply (1.15 V) before the AVDD19 (1.9 V) supply. The AVDD (1.15 V) supply can come up in any order.

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		ADC32RF44	UNIT
		RMP (VQFN)
		72 PINS
R_θJA	Junction-to-ambient thermal resistance	21.8	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	4.4	°C/W
R_θJB	Junction-to-board thermal resistance	2.0	°C/W
ψ_JT	Junction-to-top characterization parameter	0.1	°C/W
ψ_JB	Junction-to-board characterization parameter	2.0	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	0.2	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics

typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient temperature range of –40°C to +85°C; and ADC sampling rate = 2.6 GHz, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD = 1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
POWER CONSUMPTION⁽⁴⁾ (Dual-Channel Operation, Both Channels A and B are Active; DDC Bypass Mode⁽³⁾)
I_AVDD19	1.9-V analog supply current	12-bit, bypass mode, f_S = 2.6 GSPS		1730	1969	mA
I_AVDD	1.15-V analog supply current	12-bit, bypass mode, f_S = 2.6 GSPS		860	1079	mA
I_DVDD	1.15-V digital supply current	12-bit, bypass mode, f_S = 2.6 GSPS		1416	1846	mA
P_D	Power dissipation	12-bit, bypass mode, f_S = 2.6 GSPS		5.9	6.95	W
	Global power-down power dissipation			360		mW
ANALOG INPUTS
	Resolution			14		Bits
	Differential input full-scale			1.35		V_PP
V_IC	Input common-mode voltage			1.2⁽⁵⁾		V
R_IN	Input resistance	Differential resistance at dc		65		Ω
C_IN	Input capacitance	Differential capacitance at dc		2		pF
	V_CM common-mode voltage output			1.2		V
	Analog input bandwidth (–3-dB point)	ADC driven with 50-Ω source		3200		MHz
ISOLATION
	Crosstalk isolation between channel A and channel B⁽¹⁾	f_IN = 100 MHz		100		dBc
		f_IN = 900 MHz		99
		f_IN = 1800 MHz		95
		f_IN = 2700 MHz		86
		f_IN = 3500 MHz		85
CLOCK INPUT⁽²⁾
	Input clock frequency		1.5	2.6		GHz
	Differential (peak-to-peak) input clock amplitude		0.5	1.5	2.5	V_PP
	Input clock duty cycle		45%	50%	55%
	Internal clock biasing			1.0		V
	Internal clock termination (differential)			100		Ω

(1) Crosstalk is measured with a –2-dBFS input signal on aggressor channel and no input on the victim channel.

(2) See Figure 57.

(3) Full-scale signal is applied to the analog inputs of all active channels.

(4) See the Power Consumption in Different Modes section for more details.

(5) When used in dc-coupling mode, the common-mode voltage at the analog inputs should be kept within V_CM ±25 mV for best performance.

7.6 AC Performance Characteristics

typical values specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient temperature range of –40°C to +85°C; and ADC sampling rate = 2.6 GHz, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD = 1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN⁽³⁾	NOM	UNIT
SNR	Signal-to-noise ratio	f_IN = 100 MHz, A_OUT = –2 dBFS		62.5	dBFS
		f_IN = 900 MHz, A_OUT = –2 dBFS		61.2
		f_IN = 1850 MHz, A_OUT = –2 dBFS	55.5	58.3
		f_IN = 2100 MHz, A_OUT = –2 dBFS		57.5
		f_IN = 2500 MHz, A_OUT = –2 dBFS		56.4
		f_IN = 3500 MHz, A_OUT⁽²⁾ = –3 dBFS with 2-dB gain		54.0
NSD	Noise spectral density averaged across the Nyquist zone	f_IN = 100 MHz, A_OUT = –2 dBFS		153.6	dBFS/Hz
		f_IN = 900 MHz, A_OUT = –2 dBFS		152.3
		f_IN = 1850 MHz, A_OUT = –2 dBFS	146.1	149.4
		f_IN = 2100 MHz, A_OUT = –2 dBFS		148.6
		f_IN = 2500 MHz, A_OUT = –2 dBFS		147.5
		f_IN = 3500 MHz, A_OUT⁽²⁾ = –3 dBFS with 2-dB gain		145.1
	Small-signal SNR	f_IN = 1850 MHz, A_OUT = –40 dBFS		63.1	dBFS
NF⁽¹⁾	Input noise figure	f_IN = 1850 MHz, A_OUT = –40 dBFS		24.7	dB
SINAD	Signal-to-noise and distortion ratio	f_IN = 100 MHz, A_OUT = –2 dBFS		61.8	dBFS
		f_IN = 900 MHz, A_OUT = –2 dBFS		60.0
		f_IN = 1850 MHz, A_OUT = –2 dBFS		58.0
		f_IN = 2100 MHz, A_OUT = –2 dBFS		56.5
		f_IN = 2500 MHz, A_OUT = –2 dBFS		54.7
		f_IN = 3500 MHz, A_OUT⁽²⁾ = –3 dBFS with 2-dB gain		53.2
ENOB	Effective number of bits	f_IN = 100 MHz, A_OUT = –2 dBFS		10.0	Bits
		f_IN = 900 MHz, A_OUT = –2 dBFS		9.7
		f_IN = 1850 MHz, A_OUT = –2 dBFS		9.3
		f_IN = 2100 MHz, A_OUT = –2 dBFS		9.1
		f_IN = 2500 MHz, A_OUT = –2 dBFS		8.8
		f_IN = 3500 MHz, A_OUT⁽²⁾ = –3 dBFS with 2-dB gain		8.5
SFDR	Spurious-free dynamic range	f_IN = 100 MHz, A_OUT = –2 dBFS		68.0	dBc
		f_IN = 900 MHz, A_OUT = –2 dBFS		65.0
		f_IN = 1850 MHz, A_OUT = –2 dBFS	60	69.0
		f_IN = 2100 MHz, A_OUT = –2 dBFS		62.0
		f_IN = 2500 MHz, A_OUT = –2 dBFS		59.0
		f_IN = 3500 MHz, A_OUT⁽²⁾ = –3 dBFS with 2-dB gain		57.0
HD2⁽⁴⁾	Second-order harmonic distortion	f_IN = 100 MHz, A_OUT = –2 dBFS		68.0	dBc
		f_IN = 900 MHz, A_OUT = –2 dBFS		74.0
		f_IN = 1850 MHz, A_OUT = –2 dBFS	60	69.0
		f_IN = 2100 MHz, A_OUT = –2 dBFS		62.0
		f_IN = 2500 MHz, A_OUT = –2 dBFS		62.0
		f_IN = 3500 MHz, A_OUT⁽²⁾ = –3 dBFS with 2-dB gain		57.0
HD3	Third-order harmonic distortion	f_IN = 100 MHz, A_OUT = –2 dBFS		84.0	dBc
		f_IN = 900 MHz, A_OUT = –2 dBFS		65.0
		f_IN = 1850 MHz, A_OUT = –2 dBFS	62.5	74.0
		f_IN = 2100 MHz, A_OUT = –2 dBFS		67.0
		f_IN = 2500 MHz, A_OUT = –2 dBFS		59.0
		f_IN = 3500 MHz, A_OUT⁽²⁾ = –3 dBFS with 2-dB gain		72.0
HD4, HD5	Fourth- and fifth-order harmonic distortion	f_IN = 100 MHz, A_OUT = –2 dBFS		92.0	dBc
		f_IN = 900 MHz, A_OUT = –2 dBFS		82.0
		f_IN = 1850 MHz, A_OUT = –2 dBFS	69.5	86.0
		f_IN = 2100 MHz, A_OUT = –2 dBFS		87.0
		f_IN = 2500 MHz, A_OUT = –2 dBFS		90.0
		f_IN = 3500 MHz, A_OUT⁽²⁾ = –3 dBFS with 2-dB gain		87.0
IL spur	Interleaving spurs: f_S / 2 – f_IN, f_S / 4 ± f_IN	f_IN = 100 MHz, A_OUT = –2 dBFS		93.0	dBc
		f_IN = 900 MHz, A_OUT = –2 dBFS		88.0
		f_IN = 1850 MHz, A_OUT = –2 dBFS	66.5	80.0
		f_IN = 2100 MHz, A_OUT = –2 dBFS		85.0
		f_IN = 2500 MHz, A_OUT = –2 dBFS		81.0
		f_IN = 3500 MHz, A_OUT⁽²⁾ = –3 dBFS with 2-dB gain		75.0
HD2 IL	Interleaving spur for HD2: f_S / 2 – HD2	f_IN = 100 MHz, A_OUT = –2 dBFS		83.0	dBc
		f_IN = 900 MHz, A_OUT = –2 dBFS		82.0
		f_IN = 1850 MHz, A_OUT = –2 dBFS	68	80.0
		f_IN = 2100 MHz, A_OUT = –2 dBFS		75.0
		f_IN = 2500 MHz, A_OUT = –2 dBFS		77.0
		f_IN = 3500 MHz, A_OUT⁽²⁾ = –3 dBFS with 2-dB gain		77.0
Worst spur	Spurious-free dynamic range (excluding HD2, HD3, HD4, HD5, and interleaving spurs IL and HD2 IL)	f_IN = 100 MHz, A_OUT = –2 dBFS		79.0	dBc
		f_IN = 900 MHz, A_OUT = –2 dBFS		79.0
		f_IN = 1850 MHz, A_OUT = –2 dBFS		74.0
		f_IN = 2100 MHz, A_OUT = –2 dBFS		72.0
		f_IN = 2500 MHz, A_OUT = –2 dBFS		72.0
		f_IN = 3500 MHz, A_OUT⁽²⁾ = –3 dBFS with 2-dB gain		69.0
IMD3	Two-tone, third-order intermodulation distortion	f_IN1 = 900 MHz, f_IN2 = 960 MHz, A_OUT = –8 dBFS (each tone)		82	dBFS
		f_IN1 = 1850 MHz, f_IN2 = 1870 MHz, A_OUT = –8 dBFS (each tone)		72
		f_IN1 = 3490 MHz, f_IN2 = 3510 MHz, A_OUT = –8 dBFS (each tone) with 2-dB gain		69

(1) The ADC internal resistance = 65 Ω, the driving source resistance = 50 Ω.

(2) Output amplitude, A_OUT, refers to the signal amplitude in the ADC digital output that is same as the analog input amplitude, A_IN, except when the digital gain feature is used. If digital gain is G, then A_OUT = G + A_IN.

(3) Minimum values are specified at A_OUT = –3 dBFS, ADC sampling rate = 2.5 GHz.

(4) The minimum value of HD2 is specified by bench characterization.

7.7 Digital Requirements

typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient temperature range of –40°C to +85°C; and ADC sampling rate = 2.6 GHz, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD = 1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	NOM	MAX	UNIT
DIGITAL INPUTS (RESET, SCLK, SEN, SDIN, PDN, GPIO1, GPIO2, GPIO3, GPIO4)
V_IH	High-level input voltage		0.8			V
V_IL	Low-level input voltage				0.4	V
I_IH	High-level input current			50		µA
I_IL	Low-level input current			–50		µA
C_i	Input capacitance			4		pF
DIGITAL OUTPUTS (SDOUT, GPIO1, GPIO2, GPIO3, GPIO4)
V_OH	High-level output voltage		AVDD19–0.1	AVDD19		V
V_OL	Low-level output voltage				0.1	V
DIGITAL INPUTS (SYSREFP and SYSREFM; SYNCBP and SYNCBM; Requires External Biasing)
V_ID	Differential input voltage		350	450	800	mV_PP
V_CM	Input common-mode voltage		1.05	1.2	1.325	V
DIGITAL OUTPUTS (JESD204B Interface: DA[3:0], DB[3:0], Meets JESD204B LV-0IF-11G-SR Standard)
\|V_OD\|	Output differential voltage			700		mV_PP
\|V_OCM\|	Output common-mode voltage			450		mV
	Transmitter short-circuit current	Transmitter pins shorted to any voltage between –0.25 V and 1.45 V	–100		100	mA
z_os	Single-ended output impedance			50		Ω
C_o	Output capacitance	Output capacitance inside the device, from either output to ground		2		pF

7.8 Timing Requirements

typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient temperature range of –40°C to +85°C; and ADC sampling rate = 2.6 GHz, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD = 1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted)

			MIN	NOM	MAX	UNIT
SAMPLE TIMING
	Aperture delay		250		750	ps
	Aperture delay matching between two channels on the same device			±15		ps
	Aperture delay matching between two devices at the same temperature and supply voltage			±150		ps
	Aperture jitter, clock amplitude = 2 V_PP			90		f_S
Latency ⁽¹⁾⁽³⁾	Data latency, ADC sample to digital output	12-bit bypass mode, LMFS = 82820		461		Input clock cycles
Latency ⁽¹⁾⁽³⁾	Data latency, ADC sample to digital output	14-bit bypass mode, LMFS = 8224		424		Input clock cycles
	Fast overrange latency, ADC sample to FOVR indication on GPIO pins			70
t_PD	Propagation delay time: logic gates and output buffer delay (does not change with f_S)			6		ns
SYSREF TIMING⁽²⁾
t_{SU_SYSREF}	SYSREF setup time: referenced to clock rising edge, 2.6 GSPS		140	70		ps
t_{H_SYSREF}	SYSREF hold time: referenced to clock rising edge, 2.6 GSPS		50	20		ps
	Valid transition window sampling period: t_{SU_SYSREF} – t_{H_SYSREF}, 2.6 GSPS		194			ps
JESD OUTPUT INTERFACE TIMING
UI	Unit interval: 12.5 Gbps		80	100	400	ps
	Serial output data rate		2.5	10.0	12.5	Gbps
	Rise, fall times: 1-pF, single-ended load capacitance to ground			60		ps
	Total jitter: BER of 1E-15 and lane rate = 12.5 Gbps			25		%UI
	Random jitter: BER of 1E-15 and lane rate = 12.5 Gbps			0.99		%UI, rms
	Deterministic jitter: BER of 1E-15 and lane rate = 12.5 Gbps			9.1		%UI, pk-pk

(1) Overall latency = latency + t_PD.

(2) Common-mode voltage for the SYSREF input is kept at 1.2 V.

(3) Latency increases when the DDC modes are used; see Table 4.

7.9 Typical Characteristics

typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient temperature range of –40°C to +85°C; and ADC sampling rate = 2.6 GHz, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD = 1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted)

SFDR = 68 dBc, SNR = 62.7 dBFS, SINAD = 62 dBFS,
THD = 68 dBc, HD2 = –68 dBc, HD3 = –83 dBc,
SFDR (non HD2, HD3) = 74 dBc, IL spur = 83 dBc

Figure 3. FFT for 100-MHz Input Signal

SFDR = 71 dBc, SNR = 58.5 dBFS, SINAD = 58.2 dBFS,
THD = 70 dBc, HD2 = –76 dBc, HD3 = –71 dBc,
SFDR (non HD2, HD3) = 74 dBc, IL spur = 77 dBc

Figure 5. FFT for 1850-MHz Input Signal

SFDR = 59 dBc, SNR = 56.3 dBFS, SINAD = 54.2 dBFS, THD = 56 dBc, HD2 = –59 dBc, HD3 = –60 dBc, SFDR (non HD2, HD3) = 69 dBc, IL spur = 72 dBc

Figure 7. FFT for 2500-MHz Input Signal

f_IN1 = 900 MHz, f_IN2 = 960 MHz,
A_IN = –8 dBFS, IMD = 81 dBFS

Figure 9. FFT for Two-Tone Input Signal (–8 dBFS)

f_IN1 = 1850 MHz, f_IN2 = 1870 MHz,
A_IN = –8 dBFS, IMD = 74 dBFS

Figure 11. FFT for Two-Tone Input Signal (–8 dBFS)

f_IN1 = 3490 MHz, f_IN2 = 3510 MHz,
A_IN = –8 dBFS with 2-dB gain, IMD = 68 dBFS

Figure 13. FFT for Two-Tone Input Signal (–8 dBFS)

f_IN1 = 900 MHz, f_IN2 = 960 MHz

Figure 15. Intermodulation Distortion vs Input Amplitude (900 MHz and 960 MHz)

f_IN1 = 3490 MHz, f_IN2 = 3510 MHz

Figure 17. Intermodulation Distortion vs Input Amplitude (3490 MHz and 3510 MHz)

A_OUT = –2 dBFS with 0-dB gain for f_IN less than 3 GHz,
A_OUT = –3 dBFS with 2-dB gain for f_IN more than 3 GHz

Figure 19. IL Spur vs Input Frequency

f_IN = 1850 MHz, A_IN = –2 dBFS

Figure 21. Signal-to-Noise Ratio vs AVDD Supply and Temperature

f_IN = 3500 MHz, A_IN = –3 dBFS with 2-dB digital gain

Figure 23. Signal-to-Noise Ratio vs AVDD Supply and Temperature

f_IN = 1850 MHz, A_IN = –2 dBFS

Figure 25. Signal-to-Noise Ratio vs DVDD Supply and Temperature

f_IN = 3500 MHz, A_IN = –3 dBFS with 2-dB digital gain

Figure 27. Signal-to-Noise Ratio vs DVDD Supply and Temperature

f_IN = 1850 MHz, A_IN = –2 dBFS

Figure 29. Signal-to-Noise Ratio vs AVDD19 Supply and Temperature

f_IN = 3500 MHz, A_IN = –3 dBFS with 2-dB digital gain

Figure 31. Signal-to-Noise Ratio vs AVDD19 Supply and Temperature

f_IN = 1.85 GHz, A_OUT = –2 dBFS, AVDD19 = 1.8 V,
ADC sampling rate = 2.5 GHz

Figure 33. HD2 Histogram at AVDD19 = 1.8 V

f_IN = 1.85 GHz, A_OUT = –2 dBFS, AVDD19 = 2.0 V,
ADC sampling rate = 2.5 GHz

Figure 35. HD2 Histogram at AVDD19 = 2.0 V

f_IN = 3.5 GHz, 2-dB digital gain

Figure 37. Performance vs Amplitude

f_IN = 3.5 GHz, A_IN = –3 dBFS with 2-dB digital gain,
ADC sampling rate = 2.5 GHz

Figure 39. Performance vs Clock Amplitude

f_IN = 3.5 GHz, A_IN = –3 dBFS with 2-dB digital gain, ADC sampling rate = 2.5 GHz

Figure 41. Performance vs Clock Duty Cycle

ADC sampling rate = 2.5 GHz

Figure 43. Power-Supply Rejection Ratio vs Supplies

ADC sampling rate = 2.5 GHz

Figure 45. Common-Mode Rejection Ratio vs Signal Frequency

f_S = 2500 MSPS, f_IN = 1.85 GHz, A_IN = –2 dBFS,
SNR = 61 dBFS, SFDR (includes IL) = 72 dBc

Figure 47. FFT in 6X Decimation

f_S = 2500 MSPS, f_IN = 1.85 GHz, A_IN = –2 dBFS,
SNR = 61.5 dBFS, SFDR (includes IL) = 73 dBc

Figure 49. FFT in 9X Decimation

f_S = 2500 MSPS, f_IN = 1.85 GHz, A_IN = –2 dBFS,
SNR = 62.7 dBFS, SFDR (includes IL) = 80 dBc

Figure 51. FFT in 12X Decimation

f_S = 2500 MSPS, f_IN = 1.85 GHz, A_IN = –2 dBFS,
SNR = 63.2 dBFS, SFDR (includes IL) = 79 dBc

Figure 53. FFT in 18X Decimation

f_S = 2500 MSPS, f_IN = 1.85 GHz, A_IN = –2 dBFS,
SNR = 63.7 dBFS, SFDR (includes IL) = 79 dBc

Figure 55. FFT in 24X Decimation

SFDR = 63 dBc, SNR = 61.3 dBFS, SINAD = 59.8 dBFS,
THD = 63 dBc, HD2 = –72 dBc, HD3 = –63 dBc,
SFDR (non HD2, HD3) = 79 dBc, IL spur = 76 dBc

Figure 4. FFT for 900-MHz Input Signal

SFDR = 63 dBc, SNR = 57.5 dBFS, SINAD = 56.5 dBFS,
THD = 61 dBc, HD2 = –65 dBc, HD3 = –63 dBc,
SFDR (non HD2, HD3) = 72 dBc, IL spur = 72 dBc

Figure 6. FFT for 2100-MHz Input Signal

SFDR = 64 dBc, SNR = 54.1 dBFS, SINAD = 53.9 dBFS,
HD2 = –64 dBc, HD3 = –88 dBc,
SFDR (non HD2, HD3) = 72 dBc, THD = 64 dBc,
IL spur = 77 dBc, A_IN = –3 dBFS with 2-dB gain

Figure 8. FFT for 3500-MHz Input Signal

f_IN1 = 900 MHz, f_IN2 = 960 MHz,
A_IN = –36 dBFS, IMD = 96 dBFS

Figure 10. FFT for Two-Tone Input Signal (–36 dBFS)

f_IN1 = 1850 MHz, f_IN2 = 1870 MHz,
A_IN = –36 dBFS, IMD = 94 dBFS

Figure 12. FFT for Two-Tone Input Signal (–36 dBFS)

f_IN1 = 3490 MHz, f_IN2 = 3510 MHz,
A_IN = –36 dBFS with 2-dB gain, IMD = 89 dBFS

Figure 14. FFT for Two-Tone Input Signal (–36 dBFS)

f_IN1 = 1850 MHz, f_IN2 = 1870 MHz

Figure 16. Intermodulation Distortion vs Input Amplitude (1850 MHz and 1870 MHz)

A_OUT = –2 dBFS with 0-dB gain for f_IN less than 3 GHz,
A_OUT = –3 dBFS with 2-dB gain for f_IN more than 3 GHz

Figure 18. Spurious-Free Dynamic Range vs Input Frequency

A_OUT = –2 dBFS with 0-dB gain for f_IN less than 3 GHz,
A_OUT = –3 dBFS with 2-dB gain for f_IN more than 3 GHz

Figure 20. Signal-to-Noise Ratio vs Input Frequency

f_IN = 1850 MHz, A_IN = –2 dBFS

Figure 22. Spurious-Free Dynamic Range vs AVDD Supply and Temperature

f_IN = 3500 MHz, A_IN = –3 dBFS with 2-dB digital gain

Figure 24. Spurious-Free Dynamic Range vs AVDD Supply and Temperature

f_IN = 1850 MHz, A_IN = –2 dBFS

Figure 26. Spurious-Free Dynamic Range vs DVDD Supply and Temperature

f_IN = 3500 MHz, A_IN = –3 dBFS with 2-dB digital gain

Figure 28. Spurious-Free Dynamic Range vs DVDD Supply and Temperature

f_IN = 1850 MHz, A_IN = –2 dBFS

Figure 30. Spurious-Free Dynamic Range vs
AVDD19 Supply and Temperature

f_IN = 3500 MHz, A_IN = –3 dBFS with 2-dB digital gain

Figure 32. Spurious-Free Dynamic Range vs
AVDD19 Supply and Temperature

f_IN = 1.85 GHz, A_OUT = –2 dBFS, AVDD19 = 1.9 V,
ADC sampling rate = 2.5 GHz

Figure 34. HD2 Histogram at AVDD19 = 1.9 V

f_IN = 1.85 GHz

Figure 36. Performance vs Amplitude

f_IN = 1.85 GHz, A_IN = –2 dBFS,
ADC sampling rate = 2.5 GHz

Figure 38. Performance vs Clock Amplitude

f_IN = 1.85 GHz,
ADC sampling rate = 2.5 GHz

Figure 40. Performance vs Clock Duty Cycle

f_IN = 1.85 GHz, A_IN = –2 dBFS, f_PSRR = 7.5 MHz,
A_PSRR = 50 mV_PP, AVDD = 1.9 V, PSRR = 20 dB,
ADC sampling rate = 2.5 GHz

Figure 42. Power-Supply Rejection Ratio FFT for Test Signal on AVDD Supply

f_IN = 1.85 GHz, A_IN = –2 dBFS, f_CMRR = 10 MHz,
A_CSRR = 50 mV_PP, CMRR = 28 dB,
ADC sampling rate = 2.5 GHz

Figure 44. Common-Mode Rejection Ratio FFT

f_S = 2500 MSPS, f_IN = 1.85 GHz, A_IN = –2 dBFS,
SNR = 59.7 dBFS, SFDR (includes IL) = 74 dBc

Figure 46. FFT in 4X Decimation

f_S = 2500 MSPS, f_IN = 1.85 GHz, A_IN = –2 dBFS,
SNR = 61.3 dBFS, SFDR (includes IL) = 72 dBc

Figure 48. FFT in 8X Decimation

f_S = 2500 MSPS, f_IN = 1.85 GHz, A_IN = –2 dBFS,
SNR = 62 dBFS, SFDR (includes IL) = 79 dBc

Figure 50. FFT in 10X Decimation

f_S = 2500 MSPS, f_IN = 1.85 GHz, A_IN = –2 dBFS,
SNR = 63 dBFS, SFDR (includes IL) = 81 dBc

Figure 52. FFT in 16X Decimation

f_S = 2500 MSPS, f_IN = 1.85 GHz, A_IN = –2 dBFS,
SNR = 63.3 dBFS, SFDR (includes IL) = 79 dBc

Figure 54. FFT in 20X Decimation

f_S = 2500 MSPS, f_IN = 1.85 GHz, A_IN = –2 dBFS,
SNR = 63.8 dBFS, SFDR (includes IL) = 79 dBc

Figure 56. FFT in 32X Decimation

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7 Specifications

7.1 Absolute Maximum Ratings

7.2 ESD Ratings

7.3 Recommended Operating Conditions

7.4 Thermal Information

7.5 Electrical Characteristics

7.6 AC Performance Characteristics

7.7 Digital Requirements

7.8 Timing Requirements

7.9 Typical Characteristics