ZHCSG60A February   2017  – March 2017 ADC32RF44

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 AC Performance Characteristics
    7. 7.7 Digital Requirements
    8. 7.8 Timing Requirements
    9. 7.9 Typical Characteristics
  8. Parameter Measurement Information
    1. 8.1 Input Clock Diagram
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Analog Inputs
        1. 9.3.1.1 Input Clamp Circuit
      2. 9.3.2  Clock Input
      3. 9.3.3  SYSREF Input
        1. 9.3.3.1 Using SYSREF
        2. 9.3.3.2 Frequency of the SYSREF Signal
      4. 9.3.4  DDC Block
        1. 9.3.4.1 Operating Mode: Receiver
        2. 9.3.4.2 Operating Mode: Wide-Bandwidth Observation Receiver
        3. 9.3.4.3 Decimation Filters
          1. 9.3.4.3.1  Divide-by-4
          2. 9.3.4.3.2  Divide-by-6
          3. 9.3.4.3.3  Divide-by-8
          4. 9.3.4.3.4  Divide-by-9
          5. 9.3.4.3.5  Divide-by-10
          6. 9.3.4.3.6  Divide-by-12
          7. 9.3.4.3.7  Divide-by-16
          8. 9.3.4.3.8  Divide-by-18
          9. 9.3.4.3.9  Divide-by-20
          10. 9.3.4.3.10 Divide-by-24
          11. 9.3.4.3.11 Divide-by-32
          12. 9.3.4.3.12 Latency with Decimation Options
        4. 9.3.4.4 Digital Multiplexer (MUX)
        5. 9.3.4.5 Numerically-Controlled Oscillators (NCOs) and Mixers
      5. 9.3.5  NCO Switching
      6. 9.3.6  SerDes Transmitter Interface
      7. 9.3.7  Eye Diagrams
      8. 9.3.8  Alarm Outputs: Power Detectors for AGC Support
        1. 9.3.8.1 Absolute Peak Power Detector
        2. 9.3.8.2 Crossing Detector
        3. 9.3.8.3 RMS Power Detector
        4. 9.3.8.4 GPIO AGC MUX
      9. 9.3.9  Power-Down Mode
      10. 9.3.10 ADC Test Pattern
        1. 9.3.10.1 Digital Block
        2. 9.3.10.2 Transport Layer
        3. 9.3.10.3 Link Layer
    4. 9.4 Device Functional Modes
      1. 9.4.1 Device Configuration
      2. 9.4.2 JESD204B Interface
        1. 9.4.2.1 JESD204B Initial Lane Alignment (ILA)
        2. 9.4.2.2 JESD204B Frame Assembly
        3. 9.4.2.3 JESD204B Frame Assembly in Bypass Mode
        4. 9.4.2.4 JESD204B Frame Assembly with Decimation (Single-Band DDC): Complex Output
        5. 9.4.2.5 JESD204B Frame Assembly with Decimation (Single-Band DDC): Real Output
        6. 9.4.2.6 JESD204B Frame Assembly with Decimation (Single-Band DDC): Real Output
        7. 9.4.2.7 JESD204B Frame Assembly with Decimation (Dual-Band DDC): Complex Output
        8. 9.4.2.8 JESD204B Frame Assembly with Decimation (Dual-Band DDC): Real Output
      3. 9.4.3 Serial Interface
        1. 9.4.3.1 Serial Register Write: Analog Bank
        2. 9.4.3.2 Serial Register Readout: Analog Bank
        3. 9.4.3.3 Serial Register Write: Digital Bank
        4. 9.4.3.4 Serial Register Readout: Digital Bank
        5. 9.4.3.5 Serial Register Write: Decimation Filter and Power Detector Pages
    5. 9.5 Register Maps
      1. 9.5.1  Example Register Writes
      2. 9.5.2  Register Descriptions
        1. 9.5.2.1 General Registers
          1. 9.5.2.1.1 Register 000h (address = 000h), General Registers
          2. 9.5.2.1.2 Register 002h (address = 002h), General Registers
          3. 9.5.2.1.3 Register 003h (address = 003h), General Registers
          4. 9.5.2.1.4 Register 004h (address = 004h), General Registers
          5. 9.5.2.1.5 Register 010h (address = 010h), General Registers
          6. 9.5.2.1.6 Register 011h (address = 011h), General Registers
          7. 9.5.2.1.7 Register 012h (address = 012h), General Registers
      3. 9.5.3  Master Page (M = 0)
        1. 9.5.3.1 Register 020h (address = 020h), Master Page
        2. 9.5.3.2 Register 032h (address = 032h), Master Page
        3. 9.5.3.3 Register 039h (address = 039h), Master Page
        4. 9.5.3.4 Register 03Ch (address = 03Ch), Master Page
        5. 9.5.3.5 Register 05Ah (address = 05Ah), Master Page
        6. 9.5.3.6 Register 03Dh (address = 3Dh), Master Page
        7. 9.5.3.7 Register 057h (address = 057h), Master Page
        8. 9.5.3.8 Register 058h (address = 058h), Master Page
      4. 9.5.4  ADC Page (FFh, M = 0)
        1. 9.5.4.1 Register 03Fh (address = 03Fh), ADC Page
        2. 9.5.4.2 Register 042h (address = 042h), ADC Page
      5. 9.5.5  Digital Function Page (610000h, M = 1 for Channel A and 610100h, M = 1 for Channel B)
        1. 9.5.5.1 Register A6h (address = 0A6h), Digital Function Page
      6. 9.5.6  Offset Corr Page Channel A (610000h, M = 1)
        1. 9.5.6.1 Register 034h (address = 034h), Offset Corr Page Channel A
        2. 9.5.6.2 Register 068h (address = 068h), Offset Corr Page Channel A
      7. 9.5.7  Offset Corr Page Channel B (610000h, M = 1)
        1. 9.5.7.1 Register 068h (address = 068h), Offset Corr Page Channel B
      8. 9.5.8  Digital Gain Page (610005h, M = 1 for Channel A and 610105h, M = 1 for Channel B)
        1. 9.5.8.1 Register 0A6h (address = 0A6h), Digital Gain Page
      9. 9.5.9  Main Digital Page Channel A (680000h, M = 1)
        1. 9.5.9.1 Register 000h (address = 000h), Main Digital Page Channel A
        2. 9.5.9.2 Register 0A2h (address = 0A2h), Main Digital Page Channel A
      10. 9.5.10 Main Digital Page Channel B (680100h, M = 1)
        1. 9.5.10.1 Register 000h (address = 000h), Main Digital Page Channel B
        2. 9.5.10.2 Register 0A2h (address = 0A2h), Main Digital Page Channel B
      11. 9.5.11 JESD Digital Page (6900h, M = 1)
        1. 9.5.11.1  Register 001h (address = 001h), JESD Digital Page
        2. 9.5.11.2  Register 002h (address = 002h ), JESD Digital Page
        3. 9.5.11.3  Register 003h (address = 003h), JESD Digital Page
        4. 9.5.11.4  Register 004h (address = 004h), JESD Digital Page
        5. 9.5.11.5  Register 006h (address = 006h), JESD Digital Page
        6. 9.5.11.6  Register 007h (address = 007h), JESD Digital Page
        7. 9.5.11.7  Register 016h (address = 016h), JESD Digital Page
        8. 9.5.11.8  Register 017h (address = 017h), JESD Digital Page
        9. 9.5.11.9  Register 032h-035h (address = 032h-035h), JESD Digital Page
        10. 9.5.11.10 Register 036h (address = 036h), JESD Digital Page
        11. 9.5.11.11 Register 037h (address = 037h), JESD Digital Page
        12. 9.5.11.12 Register 03Eh (address = 03Eh), JESD Digital Page
      12. 9.5.12 Decimation Filter Page
        1. 9.5.12.1  Register 000h (address = 000h), Decimation Filter Page
        2. 9.5.12.2  Register 001h (address = 001h), Decimation Filter Page
        3. 9.5.12.3  Register 002h (address = 2h), Decimation Filter Page
        4. 9.5.12.4  Register 005h (address = 005h), Decimation Filter Page
        5. 9.5.12.5  Register 006h (address = 006h), Decimation Filter Page
        6. 9.5.12.6  Register 007h (address = 007h), Decimation Filter Page
        7. 9.5.12.7  Register 008h (address = 008h), Decimation Filter Page
        8. 9.5.12.8  Register 009h (address = 009h), Decimation Filter Page
        9. 9.5.12.9  Register 00Ah (address = 00Ah), Decimation Filter Page
        10. 9.5.12.10 Register 00Bh (address = 00Bh), Decimation Filter Page
        11. 9.5.12.11 Register 00Ch (address = 00Ch), Decimation Filter Page
        12. 9.5.12.12 Register 00Dh (address = 00Dh), Decimation Filter Page
        13. 9.5.12.13 Register 00Eh (address = 00Eh), Decimation Filter Page
        14. 9.5.12.14 Register 00Fh (address = 00Fh), Decimation Filter Page
        15. 9.5.12.15 Register 010h (address = 010h), Decimation Filter Page
        16. 9.5.12.16 Register 011h (address = 011h), Decimation Filter Page
        17. 9.5.12.17 Register 014h (address = 014h), Decimation Filter Page
        18. 9.5.12.18 Register 016h (address = 016h), Decimation Filter Page
        19. 9.5.12.19 Register 01Eh (address = 01Eh), Decimation Filter Page
        20. 9.5.12.20 Register 01Fh (address = 01Fh), Decimation Filter Page
        21. 9.5.12.21 Register 033h-036h (address = 033h-036h), Decimation Filter Page
        22. 9.5.12.22 Register 037h (address = 037h), Decimation Filter Page
        23. 9.5.12.23 Register 038h (address = 038h), Decimation Filter Page
        24. 9.5.12.24 Register 039h (address = 039h), Decimation Filter Page
        25. 9.5.12.25 Register 03Ah (address = 03Ah), Decimation Filter Page
      13. 9.5.13 Power Detector Page
        1. 9.5.13.1  Register 000h (address = 000h), Power Detector Page
        2. 9.5.13.2  Register 001h-002h (address = 001h-002h), Power Detector Page
        3. 9.5.13.3  Register 003h (address = 003h), Power Detector Page
        4. 9.5.13.4  Register 007h-00Ah (address = 007h-00Ah), Power Detector Page
        5. 9.5.13.5  Register 00Bh-00Ch (address = 00Bh-00Ch), Power Detector Page
        6. 9.5.13.6  Register 00Dh (address = 00Dh), Power Detector Page
        7. 9.5.13.7  Register 00Eh (address = 00Eh), Power Detector Page
        8. 9.5.13.8  Register 00Fh, 010h-012h, and 016h-019h (address = 00Fh, 010h-012h, and 016h-019h), Power Detector Page
        9. 9.5.13.9  Register 013h-01Ah (address = 013h-01Ah), Power Detector Page
        10. 9.5.13.10 Register 01Dh-01Eh (address = 01Dh-01Eh), Power Detector Page
        11. 9.5.13.11 Register 020h (address = 020h), Power Detector Page
        12. 9.5.13.12 Register 021h (address = 021h), Power Detector Page
        13. 9.5.13.13 Register 022h-025h (address = 022h-025h), Power Detector Page
        14. 9.5.13.14 Register 027h (address = 027h), Power Detector Page
        15. 9.5.13.15 Register 02Bh (address = 02Bh), Power Detector Page
        16. 9.5.13.16 Register 037h (address = 037h), Power Detector Page
        17. 9.5.13.17 Register 038h (address = 038h), Power Detector Page
        18. 9.5.13.18 Power Detector Page (Direct Addressing, 16-Bit Address, 5400h)
          1. 9.5.13.18.1 Register 032h-035h (address = 032h-035h), Power Detector Page
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Start-Up Sequence
      2. 10.1.2 Hardware Reset
      3. 10.1.3 SNR and Clock Jitter
        1. 10.1.3.1 External Clock Phase Noise Consideration
      4. 10.1.4 Power Consumption in Different Modes
      5. 10.1.5 Using DC Coupling in the ADC32RF44
        1. 10.1.5.1 Bypassing the Offset Corrector Block
          1. 10.1.5.1.1 Effect of Temperature
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Transformer-Coupled Circuits
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13器件和文档支持
    1. 13.1 文档支持
      1. 13.1.1 相关文档
    2. 13.2 接收文档更新通知
    3. 13.3 社区资源
    4. 13.4 商标
    5. 13.5 静电放电警告
    6. 13.6 Glossary
  14. 14机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
订购信息

特性

  • 14 位双通道 2.6GSPS ADC
  • 本底噪声:–154.2dBFS/Hz
  • 射频 (RF) 输入支持的频率最高可达 4.0GHz
  • 孔径抖动:90fs
  • 通道隔离:fIN = 1.8GHz 时为 95dB
  • 频谱性能(fIN = 900MHz,–2dBFS):
    • SNR:61.2dBFS
    • SFDR:65dBc(HD2、HD3)
    • SFDR:79dBc(最严重毛刺)
  • 频谱性能(fIN = 1.85GHz,–2dBFS):
    • SNR:58.3dBFS
    • SFDR:69dBc(HD2、HD3)
    • SFDR:74dBc(最严重毛刺)
  • 片上数字下变频器:
    • 最多 4 个下变频器 (DDC)(双频带模式)
    • 每个 DDC 最多配有 3 个独立数控振荡器 (NCO)
  • 提供过压保护的片上输入钳位
  • 带有报警引脚的可编程片上功率检测器,支持自动增益控制 (AGC)
  • 片上抖动
  • 片上输入端接电阻
  • 输入满量程:1.35 VPP
  • 支持多芯片同步
  • JESD204B 接口:
    • 基于子类 1 的确定性延迟
    • 12.5Gbps 时每条通道具有 4 条信道
  • 功率耗散:2.6GSPS 时为 2.95W/通道
  • 72 引脚超薄型四方扁平无引线 (VQFN) 封装 (10mm × 10mm)

应用

  • 多频带、多模式 2G、3G、4G 蜂窝接收器
  • 相控阵列雷达
  • 电子对抗战
  • 线缆基础设施
  • 无线宽带
  • 高速数字转换器
  • 软件定义无线电
  • 通信测试设备
  • 微波和毫米波接收器

说明

ADC32RF44 器件是一款 14 位 2.6GSPS 双通道模数转换器 (ADC),支持输入频率高达 4GHz 及以上的射频采样。ADC32RF44 专为高信噪比 (SNR) 设计,其噪声频谱密度为 –154.2dBFS/Hz,并可在较大输入频率范围提供动态范围和通道隔离。经缓冲的模拟输入配有片上端接电阻,可在较宽频率范围内提供统一输入阻抗并最大程度地降低采样和保持毛刺脉冲能量。

每个 ADC 通道均可连接到一个双频带数字下变频器 (DDC),每个 DDC 最多连接三个独立的 16 位数控振荡器 (NCO) 用于相位相干跳频。此外,ADC 还配有前端峰值和 RMS 功率检测器及报警功能,用以支持外部自动增益控制 (AGC) 算法。

ADC32RF44 支持具有基于子类 1 确定性延迟的 JESD204B 串行接口,其数据速率高达 12.5Gbps,每个 ADC 最多具有四条信道。该器件采用 72 引脚 VQFN 封装 (10mm × 10mm),支持工业级温度范围(-40℃ 至 +85°C)。

器件信息(1)

器件型号封装封装尺寸(标称值)
ADC32RF44VQFN (72)10.00mm x 10.00mm
  1. 要了解所有可用封装,请参见数据表末尾的可订购产品附录。

简化框图

ADC32RF44 frontpage_sbas809.gif

修订历史记录

Changes from * Revision (February 2017) to A Revision

  • Changed minimum specification of NSD parameter (fIN = 1850 MHz) from 146.6 to 146.1Go
  • Changed minimum specifications of HD3, HD4 and HD5, and IL spur parameters (fIN = 1850 MHz) from 63 to 62.5, from 70 to 69.5, and from 68 to 66.5, respectivelyGo