Altium

Design Rule Verification Report

Date: 7/21/2022
Time: 5:35:29 PM
Elapsed Time: 00:00:05
Filename: \\xle3090dm44\pds\ReferenceDesigns\PMP23001 thru 23250\PMP23126\Altium\PMP23126.1 GaN Daughter Card\RevB\PMP23126.1.PcbDoc
Warnings: 0
Rule Violations: 9

Summary

Warnings Count
Total 0

Rule Violations Count
Clearance Constraint (Gap=10mil) (InPolygon),(All) 0
Clearance Constraint (Gap=0mil) (((IsTrack Or IsArc) And Not InPoly) And IsFree and IsKeepOut),(((IsTrack Or IsArc) And Not InPoly) And IsFree and IsKeepOut) 0
Clearance Constraint (Gap=7mil) (All),(All) 0
Clearance Constraint (Gap=0mil) (IsKeepOut and InComponentClass('FiducialMark')),(IsPad and InComponentClass('FiducialMark')) 0
Clearance Constraint (Gap=50mil) (InNetClass('AC')),(Not InNetClass('AC')) 0
Clearance Constraint (Gap=10mil) (InNamedPolygon('BOTTOM_LAYER_54V1_P128')),(All) 0
Clearance Constraint (Gap=40mil) (InNetClass('HV')),(Not InNetClass('HV')) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Un-Routed Net Constraint ( (All) ) 0
Modified Polygon (Allow modified: No), (Allow shelved: No) 0
Width Constraint (Min=6mil) (Max=100mil) (Preferred=10mil) (All) 0
Routing Via (MinHoleWidth=7.874mil) (MaxHoleWidth=40mil) (PreferredHoleWidth=10mil) (MinWidth=19mil) (MaxWidth=65mil) (PreferedWidth=34mil) (All) 0
Routing Via (MinHoleWidth=7.874mil) (MaxHoleWidth=12.992mil) (PreferredHoleWidth=7.874mil) (MinWidth=19.685mil) (MaxWidth=23.622mil) (PreferedWidth=19.685mil) (IsVia and InAnyComponent) 0
Power Plane Connect Rule(Relief Connect )(Expansion=10mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All) 0
Minimum Annular Ring (Minimum=5.906mil) (IsVia and InAnyComponent) 0
Minimum Annular Ring (Minimum=4.5mil) (All) 0
Acute Angle Constraint (Minimum=45.000) (All) 0
Hole Size Constraint (Min=7.874mil) (Max=500mil) (All) 0
Hole To Hole Clearance (Gap=0mil) (All),(All) 0
Minimum Solder Mask Sliver (Gap=0.1mil) (InComponentClass('Logo')),(InComponentClass('Logo')) 0
Minimum Solder Mask Sliver (Gap=1mil) (All),(All) 0
Silk To Solder Mask (Clearance=1mil) ((IsPad or IsFill or IsRegion) and InAnycomponent),(All) 5
Silk To Solder Mask (Clearance=1mil) (All),(All) 4
Silk to Silk (Clearance=0mil) ((HasFootprint('Pb-Free_Overlay_Medium') OR HasFootprint('Pb-Free_Overlay_Small'))),((HasFootprint('Pb-Free_Overlay_Medium') OR HasFootprint('Pb-Free_Overlay_Small'))) 0
Silk to Silk (Clearance=1mil) (All),(All) 0
Net Antennae (Tolerance=0mil) (All) 0
Board Clearance Constraint (Gap=0mil) (OnCopper and Not InComponentClass('Logo') and not InComponentClass('FiducialMark') and not InRegion(1000,500,4000,800) and not InPoly) 0
Board Clearance Constraint (Gap=0mil) (OnCopper and IsPoly) 0
Board Clearance Constraint (Gap=0mil) (OnCopper and InComponentClass('Mounting Holes')) 0
Component Clearance Constraint ( Horizontal Gap = 5mil, Vertical Gap = 10mil ) ((HasFootprint('NY PMS 440 0025 PH'))),((HasFootprint('Keystone_1902C'))) 0
Component Clearance Constraint ( Horizontal Gap = 50mil, Vertical Gap = Infinite ) (InComponentClass('Mounting Holes')),(All) 0
Component Clearance Constraint ( Horizontal Gap = 10mil, Vertical Gap = 10mil ) (InComponentClass('Logo')),(All) 0
Component Clearance Constraint ( Horizontal Gap = 50mil, Vertical Gap = 10mil ) (InComponentClass('Mounting Holes')),(InComponentClass('FiducialMark')) 0
Component Clearance Constraint ( Horizontal Gap = 0mil, Vertical Gap = 0mil ) (InComponentClass('Header')),(InComponentClass('Shunt')) 0
Component Clearance Constraint ( Horizontal Gap = 10mil, Vertical Gap = 10mil ) (IsThruComponent),(IsThruComponent) 0
Component Clearance Constraint ( Horizontal Gap = 10mil, Vertical Gap = 10mil ) (All),(All) 0
Component Clearance Constraint ( Horizontal Gap = 5mil, Vertical Gap = 10mil ) (HasFootprint('0201*') or HasFootprint('0402*') or HasFootprint('0508') or HasFootprint('0603*') or HasFootprint('0612') or HasFootprint('0805*') or HasFootprint('0815*') or HasFootprint('0830*') or HasFootprint('1206*') or HasFootprint('1210*') or HasFootprint('1808*') or HasFootprint('1812*') or HasFootprint('1825*') or HasFootprint('2010*') or HasFootprint('2220*') or HasFootprint('2225*') or HasFootprint('2512*') or HasFootprint('2728*') or HasFootprint('3518*')),(HasFootprint('0201*') or HasFootprint('0402*') or HasFootprint('0508') or HasFootprint('0603*') or HasFootprint('0612') or HasFootprint('0805*') or HasFootprint('0815*') or HasFootprint('0830*') or HasFootprint('1206*') or HasFootprint('1210*') or HasFootprint('1808*') or HasFootprint('1812*') or HasFootprint('1825*') or HasFootprint('2010*') or HasFootprint('2220*') or HasFootprint('2225*') or HasFootprint('2512*') or HasFootprint('2728*') or HasFootprint('3518*')) 0
Component Clearance Constraint ( Horizontal Gap = 10mil, Vertical Gap = 10mil ) (IsThruComponent),(IsSMTComponent) 0
Height Constraint (Min=0mil) (Max=1500mil) (Prefered=500mil) (All) 0
Total 9

Silk To Solder Mask (Clearance=1mil) ((IsPad or IsFill or IsRegion) and InAnycomponent),(All)
Silk To Solder Mask Clearance Constraint: (Collision < 1mil) Between Arc (930.567mil,650.434mil) on Bottom Overlay And Pad U5-42(930.567mil,620.85mil) on Bottom Layer [Bottom Overlay] to [Bottom Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 1mil) Between Pad C10-1(849.624mil,614.315mil) on Top Layer And Track (789.937mil,600.425mil)(886.394mil,600.425mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 1mil) Between Pad C18-2(820.933mil,614.315mil) on Top Layer And Track (789.937mil,600.425mil)(886.394mil,600.425mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 1mil) Between Pad C20-1(919.185mil,650.82mil) on Top Layer And Track (888.105mil,657.384mil)(970.782mil,657.384mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 1mil) Between Pad C20-2(879.815mil,650.82mil) on Top Layer And Track (888.105mil,657.384mil)(970.782mil,657.384mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]

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Silk To Solder Mask (Clearance=1mil) (All),(All)
Silk To Solder Mask Clearance Constraint: (Collision < 1mil) Between Track (707.927mil,1104.591mil)(778.794mil,1104.591mil) on Top Overlay And Via (699.939mil,1089.966mil) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 1mil) Between Track (707.927mil,1104.591mil)(778.794mil,1104.591mil) on Top Overlay And Via (725.939mil,1089.966mil) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 1mil) Between Track (707.927mil,1104.591mil)(778.794mil,1104.591mil) on Top Overlay And Via (751.939mil,1089.966mil) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 1mil) Between Track (707.927mil,1104.591mil)(778.794mil,1104.591mil) on Top Overlay And Via (777.939mil,1089.966mil) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [0mil]

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