Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:12.4 (ISE) - M.81d Target Family: Virtex4
OS Platform: NT Target Device: xc4vlx25
Project ID (random number) 1cccf70105274338afc8504c95922ec2.31D7AF4A31F04599B2550A627B666D00.16 Target Package: ff668
Registration ID 176198637_176198648_669 Target Speed: -11
Date Generated 2011-01-27T16:02:47 Tool Flow ISE
 
User Environment
OS Name Microsoft Windows XP Professional OS Release Service Pack 3 (build 2600)
CPU Name Intel(R) Core(TM)2 Quad CPU Q9505 @ 2.83GHz CPU Speed 2826 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Counters=4
  • 16-bit down counter=1
  • 17-bit up counter=1
  • 21-bit up counter=1
  • 3-bit up counter=1
FSMs=4 Multiplexers=11
  • 1-bit 8-to-1 multiplexer=8
  • 8-bit 8-to-1 multiplexer=2
  • 96-bit 8-to-1 multiplexer=1
Registers=543
  • Flip-Flops=543
Xors=1
  • 1-bit xor2=1
MiscellaneousStatistics
  • AGG_BONDED_IO=186
  • AGG_IO=186
  • AGG_SLICE=1121
  • NUM_4_INPUT_LUT=1022
  • NUM_BONDED_IOB=186
  • NUM_BUFG=7
  • NUM_BUFGCTRL=1
  • NUM_CYMUX=143
  • NUM_DCM_ADV=4
  • NUM_ILOGIC=49
  • NUM_IOB_FF=97
  • NUM_LUT_RT=68
  • NUM_OLOGIC=3
  • NUM_RAMB16=44
  • NUM_SLICEL=1121
  • NUM_SLICE_FF=950
  • NUM_XOR=102
  • Xilinx Core fifo_generator_v5_3, Xilinx CORE Generator 12.4=2
NetStatistics
  • NumNets_Active=2453
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BOUNCEIN=1227
  • NumNodesOfType_Active_BUFGOUT=8
  • NumNodesOfType_Active_CLKPIN=912
  • NumNodesOfType_Active_CNTRLPIN=1106
  • NumNodesOfType_Active_DOUBLE=7850
  • NumNodesOfType_Active_GENERIC=20
  • NumNodesOfType_Active_GLOBAL=311
  • NumNodesOfType_Active_HLONG=94
  • NumNodesOfType_Active_HUNIHEX=1053
  • NumNodesOfType_Active_INPUT=5528
  • NumNodesOfType_Active_IOBIN2OUT=85
  • NumNodesOfType_Active_IOBINPUT=35
  • NumNodesOfType_Active_IOBOUTPUT=120
  • NumNodesOfType_Active_OMUX=1860
  • NumNodesOfType_Active_OUTBOUND=2006
  • NumNodesOfType_Active_OUTPUT=2051
  • NumNodesOfType_Active_PADINPUT=87
  • NumNodesOfType_Active_PADOUTPUT=137
  • NumNodesOfType_Active_PINBOUNCE=1689
  • NumNodesOfType_Active_PINFEED=6614
  • NumNodesOfType_Active_VLONG=93
  • NumNodesOfType_Active_VUNIHEX=1402
  • NumNodesOfType_Vcc_HVCCOUT=4
  • NumNodesOfType_Vcc_INPUT=23
  • NumNodesOfType_Vcc_IOBINPUT=51
  • NumNodesOfType_Vcc_IOBOUTPUT=3
  • NumNodesOfType_Vcc_KVCCOUT=66
  • NumNodesOfType_Vcc_PADINPUT=3
  • NumNodesOfType_Vcc_PINBOUNCE=12
  • NumNodesOfType_Vcc_PINFEED=62
SiteStatistics
  • BUFG-BUFGCTRL=7
  • ILOGIC-ISERDES=49
  • IOB-IOBM=66
  • IOB-IOBS=69
  • IOB-LOWCAPIOB=51
  • OLOGIC-OSERDES=3
  • SLICEL-SLICEM=552
SiteSummary
  • BUFG=7
  • BUFGCTRL=1
  • BUFGCTRL_BUFGCTRL=1
  • BUFG_GCLK_BUFFER=7
  • DCM_ADV=8
  • DCM_ADV_DCM_ADV=8
  • ILOGIC=49
  • ILOGIC_IFF1=49
  • ILOGIC_IFF3=48
  • IOB=186
  • IOB_INBUF=112
  • IOB_OUTBUF=30
  • IOB_PAD=186
  • IOB_PADOUTUSED=52
  • OLOGIC=3
  • OLOGIC_O1USED=3
  • PMV=1
  • PMV_PMV=1
  • RAMB16=44
  • RAMB16_RAMB16=44
  • SLICEL=1121
  • SLICEL_C1VDD=9
  • SLICEL_C2VDD=7
  • SLICEL_CYMUXF=74
  • SLICEL_CYMUXG=69
  • SLICEL_F=543
  • SLICEL_F5MUX=91
  • SLICEL_F6MUX=24
  • SLICEL_FFX=217
  • SLICEL_FFY=733
  • SLICEL_G=479
  • SLICEL_GNDF=65
  • SLICEL_GNDG=62
  • SLICEL_XORF=52
  • SLICEL_XORG=50
 
Configuration Data
BUFGCTRL
  • CE0=[CE0_INV:1] [CE0:0]
  • CE1=[CE1_INV:0] [CE1:1]
  • IGNORE0=[IGNORE0:1] [IGNORE0_INV:0]
  • IGNORE1=[IGNORE1:1] [IGNORE1_INV:0]
  • S0=[S0:1] [S0_INV:0]
  • S1=[S1_INV:0] [S1:1]
BUFGCTRL_BUFGCTRL
  • CE0=[CE0_INV:1] [CE0:0]
  • CE1=[CE1_INV:0] [CE1:1]
  • CREATE_EDGE=[TRUE:1]
  • IGNORE0=[IGNORE0:1] [IGNORE0_INV:0]
  • IGNORE1=[IGNORE1:1] [IGNORE1_INV:0]
  • INIT_OUT=[0:1]
  • PRESELECT_I0=[TRUE:1]
  • PRESELECT_I1=[FALSE:1]
  • S0=[S0:1] [S0_INV:0]
  • S1=[S1_INV:0] [S1:1]
DCM_ADV
  • CTLMODE=[CTLMODE:4] [CTLMODE_INV:0]
  • DADDR0=[DADDR0_INV:0] [DADDR0:4]
  • DADDR1=[DADDR1_INV:0] [DADDR1:4]
  • DADDR2=[DADDR2_INV:0] [DADDR2:4]
  • DADDR3=[DADDR3_INV:0] [DADDR3:4]
  • DADDR4=[DADDR4:4] [DADDR4_INV:0]
  • DADDR5=[DADDR5_INV:0] [DADDR5:4]
  • DADDR6=[DADDR6_INV:0] [DADDR6:4]
  • DEN=[DEN:4] [DEN_INV:0]
  • DI0=[DI0_INV:0] [DI0:4]
  • DI1=[DI1_INV:0] [DI1:4]
  • DI10=[DI10:4] [DI10_INV:0]
  • DI11=[DI11:4] [DI11_INV:0]
  • DI12=[DI12:4] [DI12_INV:0]
  • DI13=[DI13:4] [DI13_INV:0]
  • DI14=[DI14:4] [DI14_INV:0]
  • DI15=[DI15:4] [DI15_INV:0]
  • DI2=[DI2_INV:0] [DI2:4]
  • DI3=[DI3_INV:0] [DI3:4]
  • DI4=[DI4_INV:0] [DI4:4]
  • DI5=[DI5_INV:0] [DI5:4]
  • DI6=[DI6_INV:0] [DI6:4]
  • DI7=[DI7_INV:0] [DI7:4]
  • DI8=[DI8_INV:0] [DI8:4]
  • DI9=[DI9_INV:0] [DI9:4]
  • DWE=[DWE:4] [DWE_INV:0]
  • PSEN=[PSEN_INV:4] [PSEN:4]
  • PSINCDEC=[PSINCDEC_INV:0] [PSINCDEC:4]
  • RST=[RST:4] [RST_INV:0]
DCM_ADV_DCM_ADV
  • BGM_CONFIG_REF_SEL=[CLKIN:8]
  • BGM_DIVIDE=[16:8]
  • BGM_LDLY=[5:8]
  • BGM_MODE=[BG_SNAPSHOT:8]
  • BGM_MULTIPLY=[16:8]
  • BGM_SAMPLE_LEN=[2:8]
  • BGM_SDLY=[3:8]
  • BGM_VADJ=[5:8]
  • BGM_VLDLY=[7:8]
  • BGM_VSDLY=[0:8]
  • CLKDV_DIVIDE=[16.0:1] [4.0:2] [2.0:5]
  • CLKFX_DIVIDE=[1:8]
  • CLKFX_MULTIPLY=[4:8]
  • CLKIN_DIVIDE_BY_2=[FALSE:4] [TRUE:4]
  • CLKOUT_PHASE_SHIFT=[FIXED:8]
  • CLK_FEEDBACK=[1X:8]
  • CTLMODE=[CTLMODE:4] [CTLMODE_INV:0]
  • DADDR0=[DADDR0_INV:0] [DADDR0:4]
  • DADDR1=[DADDR1_INV:0] [DADDR1:4]
  • DADDR2=[DADDR2_INV:0] [DADDR2:4]
  • DADDR3=[DADDR3_INV:0] [DADDR3:4]
  • DADDR4=[DADDR4:4] [DADDR4_INV:0]
  • DADDR5=[DADDR5_INV:0] [DADDR5:4]
  • DADDR6=[DADDR6_INV:0] [DADDR6:4]
  • DCM_CLKDV_CLKFX_ALIGNMENT=[TRUE:8]
  • DCM_EXT_FB_EN=[FALSE:8]
  • DCM_LOCK_HIGH=[FALSE:8]
  • DCM_PERFORMANCE_MODE=[MAX_SPEED:8]
  • DCM_UNUSED_TAPS_POWERDOWN=[FALSE:4] [TRUE:4]
  • DCM_VREF_SOURCE=[VBG_DLL:8]
  • DCM_VREG_ENABLE=[FALSE:4] [TRUE:4]
  • DEN=[DEN:4] [DEN_INV:0]
  • DESKEW_ADJUST=[0:2] [17:6]
  • DFS_AVE_FREQ_ADJ_INTERVAL=[3:8]
  • DFS_AVE_FREQ_GAIN=[2.0:8]
  • DFS_AVE_FREQ_SAMPLE_INTERVAL=[2:8]
  • DFS_COARSE_SEL=[LEGACY:8]
  • DFS_EARLY_LOCK=[FALSE:8]
  • DFS_EN_RELRST=[TRUE:8]
  • DFS_EXTEND_FLUSH_TIME=[FALSE:8]
  • DFS_EXTEND_HALT_TIME=[FALSE:8]
  • DFS_EXTEND_RUN_TIME=[FALSE:8]
  • DFS_FINE_SEL=[LEGACY:8]
  • DFS_FREQUENCY_MODE=[LOW:8]
  • DFS_NON_STOP=[FALSE:8]
  • DFS_OSCILLATOR_MODE=[PHASE_FREQ_LOCK:8]
  • DFS_SKIP_FINE=[FALSE:8]
  • DFS_TP_SEL=[LEVEL:8]
  • DFS_TRACKMODE=[1:8]
  • DI0=[DI0_INV:0] [DI0:4]
  • DI1=[DI1_INV:0] [DI1:4]
  • DI10=[DI10:4] [DI10_INV:0]
  • DI11=[DI11:4] [DI11_INV:0]
  • DI12=[DI12:4] [DI12_INV:0]
  • DI13=[DI13:4] [DI13_INV:0]
  • DI14=[DI14:4] [DI14_INV:0]
  • DI15=[DI15:4] [DI15_INV:0]
  • DI2=[DI2_INV:0] [DI2:4]
  • DI3=[DI3_INV:0] [DI3:4]
  • DI4=[DI4_INV:0] [DI4:4]
  • DI5=[DI5_INV:0] [DI5:4]
  • DI6=[DI6_INV:0] [DI6:4]
  • DI7=[DI7_INV:0] [DI7:4]
  • DI8=[DI8_INV:0] [DI8:4]
  • DI9=[DI9_INV:0] [DI9:4]
  • DLL_CONTROL_CLOCK_SPEED=[HALF:8]
  • DLL_CTL_SEL_CLKIN_DIV2=[FALSE:8]
  • DLL_DESKEW_LOCK_BY1=[FALSE:8]
  • DLL_FREQUENCY_MODE=[HIGH:2] [LOW:6]
  • DLL_PD_DLY_SEL=[0:8]
  • DLL_PERIOD_LOCK_BY1=[FALSE:8]
  • DLL_PHASE_DETECTOR_AUTO_RESET=[TRUE:8]
  • DLL_PHASE_DETECTOR_MODE=[ENHANCED:8]
  • DLL_PHASE_SHIFT_CALIBRATION=[AUTO_DPS:8]
  • DLL_PHASE_SHIFT_LOCK_BY1=[FALSE:8]
  • DUTY_CYCLE_CORRECTION=[TRUE:8]
  • DWE=[DWE:4] [DWE_INV:0]
  • PMCD_SYNC=[FALSE:8]
  • PSEN=[PSEN_INV:4] [PSEN:4]
  • PSINCDEC=[PSINCDEC_INV:0] [PSINCDEC:4]
  • RST=[RST:4] [RST_INV:0]
  • STARTUP_WAIT=[FALSE:8]
ILOGIC
  • CE1=[CE1_INV:0] [CE1:48]
  • CLK=[CLK:49] [CLK_INV:0]
  • REV=[REV_INV:0] [REV:48]
  • SR=[SR:48] [SR_INV:0]
ILOGIC_IFF1
  • CE=[CE:48] [CE_INV:0]
  • CK=[CK:49] [CK_INV:0]
  • INIT_Q1=[0:49]
  • LATCH_OR_FF=[FF:49]
  • REV=[REV_INV:0] [REV:48]
  • SR=[SR:48] [SR_INV:0]
  • SRTYPE=[SYNC:48]
  • SRVAL_Q1=[0:48]
ILOGIC_IFF3
  • CE=[CE:48] [CE_INV:0]
  • CK=[CK:48] [CK_INV:0]
  • INIT_Q3=[0:48]
  • REV=[REV_INV:0] [REV:48]
  • SR=[SR:48] [SR_INV:0]
  • SRTYPE=[SYNC:48]
  • SRVAL_Q3=[0:48]
IOB_PAD
  • DIFF_TERM=[TRUE:104]
  • DRIVEATTRBOX=[12:30]
  • IOATTRBOX=[LVDS_25:104] [LVCMOS18:6] [LVCMOS25:14] [LVCMOS33:62]
  • SLEW=[SLOW:30]
OLOGIC
  • D1=[D1:0] [D1_INV:3]
OLOGIC_O1USED
  • 0=[0:0] [0_INV:3]
RAMB16
  • CLKA=[CLKA_INV:0] [CLKA:44]
  • CLKB=[CLKB_INV:0] [CLKB:44]
  • ENA=[ENA_INV:12] [ENA:32]
  • ENB=[ENB_INV:0] [ENB:44]
  • REGCEA=[REGCEA_INV:0] [REGCEA:44]
  • REGCEB=[REGCEB_INV:0] [REGCEB:44]
  • SSRA=[SSRA_INV:0] [SSRA:44]
  • SSRB=[SSRB_INV:0] [SSRB:44]
  • WEA0=[WEA0:0] [WEA0_INV:44]
  • WEA1=[WEA1:0] [WEA1_INV:44]
  • WEA2=[WEA2:0] [WEA2_INV:44]
  • WEA3=[WEA3_INV:44] [WEA3:0]
  • WEB0=[WEB0:44] [WEB0_INV:0]
  • WEB1=[WEB1:44] [WEB1_INV:0]
  • WEB2=[WEB2_INV:0] [WEB2:44]
  • WEB3=[WEB3:44] [WEB3_INV:0]
RAMB16_RAMB16
  • CLKA=[CLKA_INV:0] [CLKA:44]
  • CLKB=[CLKB_INV:0] [CLKB:44]
  • DOA_REG=[0:44]
  • DOB_REG=[0:44]
  • ENA=[ENA_INV:12] [ENA:32]
  • ENB=[ENB_INV:0] [ENB:44]
  • EN_ECC_READ=[FALSE:44]
  • EN_ECC_WRITE=[FALSE:44]
  • INVERT_CLK_DOA_REG=[FALSE:44]
  • INVERT_CLK_DOB_REG=[FALSE:44]
  • RAM_EXTENSION_A=[NONE:44]
  • RAM_EXTENSION_B=[NONE:44]
  • READ_WIDTH_A=[4:12] [9:32]
  • READ_WIDTH_B=[4:12] [9:32]
  • REGCEA=[REGCEA_INV:0] [REGCEA:44]
  • REGCEB=[REGCEB_INV:0] [REGCEB:44]
  • SAVEDATA=[FALSE:44]
  • SSRA=[SSRA_INV:0] [SSRA:44]
  • SSRB=[SSRB_INV:0] [SSRB:44]
  • WEA0=[WEA0:0] [WEA0_INV:44]
  • WEA1=[WEA1:0] [WEA1_INV:44]
  • WEA2=[WEA2:0] [WEA2_INV:44]
  • WEA3=[WEA3_INV:44] [WEA3:0]
  • WEB0=[WEB0:44] [WEB0_INV:0]
  • WEB1=[WEB1:44] [WEB1_INV:0]
  • WEB2=[WEB2_INV:0] [WEB2:44]
  • WEB3=[WEB3:44] [WEB3_INV:0]
  • WRITE_MODE_A=[READ_FIRST:44]
  • WRITE_MODE_B=[READ_FIRST:44]
  • WRITE_WIDTH_A=[4:12] [9:32]
  • WRITE_WIDTH_B=[4:12] [9:32]
SLICEL
  • BX=[BX_INV:1] [BX:224]
  • BY=[BY:612] [BY_INV:0]
  • CE=[CE:154] [CE_INV:45]
  • CIN=[CIN_INV:0] [CIN:61]
  • CLK=[CLK:759] [CLK_INV:0]
  • SR=[SR:727] [SR_INV:0]
SLICEL_CYMUXF
  • 0=[0:74] [0_INV:0]
  • 1=[1_INV:1] [1:73]
SLICEL_CYMUXG
  • 0=[0:69] [0_INV:0]
SLICEL_F5MUX
  • S0=[S0:91] [S0_INV:0]
SLICEL_F6MUX
  • S0=[S0:24] [S0_INV:0]
SLICEL_FFX
  • CE=[CE:44] [CE_INV:27]
  • CK=[CK:217] [CK_INV:0]
  • D=[D:217] [D_INV:0]
  • FFX_INIT_ATTR=[INIT0:206] [INIT1:11]
  • FFX_SR_ATTR=[SRLOW:206] [SRHIGH:11]
  • LATCH_OR_FF=[FF:217]
  • SR=[SR:213] [SR_INV:0]
  • SYNC_ATTR=[ASYNC:217]
SLICEL_FFY
  • CE=[CE:152] [CE_INV:45]
  • CK=[CK:733] [CK_INV:0]
  • D=[D:733] [D_INV:0]
  • FFY_INIT_ATTR=[INIT0:712] [INIT1:21]
  • FFY_SR_ATTR=[SRLOW:712] [SRHIGH:21]
  • LATCH_OR_FF=[FF:733]
  • SR=[SR:701] [SR_INV:0]
  • SYNC_ATTR=[ASYNC:733]
SLICEL_XORF
  • 1=[1_INV:1] [1:51]
 
Pin Data
BUFG
  • I0=7
  • O=7
BUFGCTRL
  • CE0=1
  • CE1=1
  • I0=1
  • I1=1
  • IGNORE0=1
  • IGNORE1=1
  • O=1
  • S0=1
  • S1=1
BUFGCTRL_BUFGCTRL
  • CE0=1
  • CE1=1
  • I0=1
  • I1=1
  • IGNORE0=1
  • IGNORE1=1
  • O=1
  • S0=1
  • S1=1
BUFG_GCLK_BUFFER
  • IN=7
  • OUT=7
DCM_ADV
  • CLK0=8
  • CLKDV=3
  • CLKFB=8
  • CLKIN=8
  • CTLMODE=4
  • DADDR0=4
  • DADDR1=4
  • DADDR2=4
  • DADDR3=4
  • DADDR4=4
  • DADDR5=4
  • DADDR6=4
  • DCLK=4
  • DEN=4
  • DI0=4
  • DI1=4
  • DI10=4
  • DI11=4
  • DI12=4
  • DI13=4
  • DI14=4
  • DI15=4
  • DI2=4
  • DI3=4
  • DI4=4
  • DI5=4
  • DI6=4
  • DI7=4
  • DI8=4
  • DI9=4
  • DWE=4
  • LOCKED=2
  • PSCLK=4
  • PSEN=8
  • PSINCDEC=4
  • RST=4
DCM_ADV_DCM_ADV
  • CLK0=8
  • CLKDV=3
  • CLKFB=8
  • CLKIN=8
  • CTLMODE=4
  • DADDR0=4
  • DADDR1=4
  • DADDR2=4
  • DADDR3=4
  • DADDR4=4
  • DADDR5=4
  • DADDR6=4
  • DCLK=4
  • DEN=4
  • DI0=4
  • DI1=4
  • DI10=4
  • DI11=4
  • DI12=4
  • DI13=4
  • DI14=4
  • DI15=4
  • DI2=4
  • DI3=4
  • DI4=4
  • DI5=4
  • DI6=4
  • DI7=4
  • DI8=4
  • DI9=4
  • DWE=4
  • LOCKED=2
  • PSCLK=4
  • PSEN=8
  • PSINCDEC=4
  • RST=4
ILOGIC
  • CE1=48
  • CLK=49
  • D=49
  • Q1=49
  • REV=48
  • SR=48
ILOGIC_IFF1
  • CE=48
  • CK=49
  • D=49
  • Q=49
  • REV=48
  • SR=48
ILOGIC_IFF3
  • CE=48
  • CK=48
  • D=48
  • Q=48
  • REV=48
  • SR=48
IOB
  • DIFFI_IN=52
  • I=112
  • O=30
  • PAD=186
  • PADOUT=52
  • T=8
IOB_INBUF
  • DIFFI_IN=52
  • OUT=112
  • PAD=112
IOB_OUTBUF
  • IN=30
  • OUT=30
  • TRI=8
IOB_PAD
  • PAD=186
IOB_PADOUTUSED
  • 0=52
  • OUT=52
OLOGIC
  • D1=3
  • OQ=3
OLOGIC_O1USED
  • 0=3
  • OUT=3
PMV
  • A0=1
  • A1=1
  • A2=1
  • A3=1
  • A4=1
  • A5=1
  • EN=1
  • ODIV4=1
PMV_PMV
  • A0=1
  • A1=1
  • A2=1
  • A3=1
  • A4=1
  • A5=1
  • EN=1
  • ODIV4=1
RAMB16
  • ADDRA10=44
  • ADDRA11=44
  • ADDRA12=44
  • ADDRA13=44
  • ADDRA2=12
  • ADDRA3=44
  • ADDRA4=44
  • ADDRA5=44
  • ADDRA6=44
  • ADDRA7=44
  • ADDRA8=44
  • ADDRA9=44
  • ADDRB10=44
  • ADDRB11=44
  • ADDRB12=44
  • ADDRB13=44
  • ADDRB2=12
  • ADDRB3=44
  • ADDRB4=44
  • ADDRB5=44
  • ADDRB6=44
  • ADDRB7=44
  • ADDRB8=44
  • ADDRB9=44
  • CLKA=44
  • CLKB=44
  • DIA0=44
  • DIA1=44
  • DIA2=44
  • DIA3=44
  • DIA4=32
  • DIA5=32
  • DIA6=32
  • DIA7=32
  • DIB0=44
  • DIB1=44
  • DIB2=44
  • DIB3=44
  • DIB4=32
  • DIB5=32
  • DIB6=32
  • DIB7=32
  • DIPA0=32
  • DIPB0=32
  • DOB0=44
  • DOB1=44
  • DOB2=44
  • DOB3=44
  • DOB4=32
  • DOB5=32
  • DOB6=32
  • DOB7=32
  • DOPB0=32
  • ENA=44
  • ENB=44
  • REGCEA=44
  • REGCEB=44
  • SSRA=44
  • SSRB=44
  • WEA0=44
  • WEA1=44
  • WEA2=44
  • WEA3=44
  • WEB0=44
  • WEB1=44
  • WEB2=44
  • WEB3=44
RAMB16_RAMB16
  • ADDRA10=44
  • ADDRA11=44
  • ADDRA12=44
  • ADDRA13=44
  • ADDRA2=12
  • ADDRA3=44
  • ADDRA4=44
  • ADDRA5=44
  • ADDRA6=44
  • ADDRA7=44
  • ADDRA8=44
  • ADDRA9=44
  • ADDRB10=44
  • ADDRB11=44
  • ADDRB12=44
  • ADDRB13=44
  • ADDRB2=12
  • ADDRB3=44
  • ADDRB4=44
  • ADDRB5=44
  • ADDRB6=44
  • ADDRB7=44
  • ADDRB8=44
  • ADDRB9=44
  • CLKA=44
  • CLKB=44
  • DIA0=44
  • DIA1=44
  • DIA2=44
  • DIA3=44
  • DIA4=32
  • DIA5=32
  • DIA6=32
  • DIA7=32
  • DIB0=44
  • DIB1=44
  • DIB2=44
  • DIB3=44
  • DIB4=32
  • DIB5=32
  • DIB6=32
  • DIB7=32
  • DIPA0=32
  • DIPB0=32
  • DOB0=44
  • DOB1=44
  • DOB2=44
  • DOB3=44
  • DOB4=32
  • DOB5=32
  • DOB6=32
  • DOB7=32
  • DOPB0=32
  • ENA=44
  • ENB=44
  • REGCEA=44
  • REGCEB=44
  • SSRA=44
  • SSRB=44
  • WEA0=44
  • WEA1=44
  • WEA2=44
  • WEA3=44
  • WEB0=44
  • WEB1=44
  • WEB2=44
  • WEB3=44
SLICEL
  • BX=225
  • BY=612
  • CE=199
  • CIN=61
  • CLK=759
  • COUT=69
  • F1=541
  • F2=505
  • F3=475
  • F4=154
  • F5=48
  • FXINA=24
  • FXINB=24
  • G1=478
  • G2=442
  • G3=369
  • G4=126
  • SR=727
  • X=336
  • XMUX=39
  • XQ=217
  • Y=251
  • YQ=733
SLICEL_C1VDD
  • 1=9
SLICEL_C2VDD
  • 1=7
SLICEL_CYMUXF
  • 0=74
  • 1=74
  • OUT=74
  • S0=74
SLICEL_CYMUXG
  • 0=69
  • 1=69
  • OUT=69
  • S0=69
SLICEL_F
  • A1=541
  • A2=505
  • A3=475
  • A4=154
  • D=543
SLICEL_F5MUX
  • 0=91
  • 1=91
  • OUT=91
  • S0=91
SLICEL_F6MUX
  • 0=24
  • 1=24
  • OUT=24
  • S0=24
SLICEL_FFX
  • CE=71
  • CK=217
  • D=217
  • Q=217
  • SR=213
SLICEL_FFY
  • CE=197
  • CK=733
  • D=733
  • Q=733
  • SR=701
SLICEL_G
  • A1=478
  • A2=442
  • A3=369
  • A4=126
  • D=479
SLICEL_GNDF
  • 0=65
SLICEL_GNDG
  • 0=62
SLICEL_XORF
  • 0=52
  • 1=52
  • O=52
SLICEL_XORG
  • 0=50
  • 1=50
  • O=50
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <ise_file> <fname>.ngd
  • map -intstyle ise -p xc4vlx25-ff668-11 -timing -logic_opt off -ol high -t 1 -register_duplication off -global_opt off -cm area -ir off -pr off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 11 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <ise_file> <fname>.ngd
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <ise_file> <fname>.ngd
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <ise_file> <fname>.ngd
  • map -intstyle ise -p xc4vlx25-ff668-11 -timing -logic_opt off -ol high -t 1 -register_duplication off -global_opt off -cm area -ir off -pr off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 11 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <ise_file> <fname>.ngd
  • map -intstyle ise -p xc4vlx25-ff668-11 -timing -logic_opt off -ol high -t 1 -register_duplication off -global_opt off -cm area -ir off -pr off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 11 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <ise_file> <fname>.ngd
  • map -intstyle ise -p xc4vlx25-ff668-11 -timing -logic_opt off -ol high -t 1 -register_duplication off -global_opt off -cm area -ir off -pr off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 11 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <ise_file> <fname>.ngd
  • map -intstyle ise -p xc4vlx25-ff668-11 -timing -logic_opt off -ol high -t 1 -register_duplication off -global_opt off -cm area -ir off -pr off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 11 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <ise_file> <fname>.ngd
  • map -intstyle ise -p xc4vlx25-ff668-11 -timing -logic_opt off -ol high -t 1 -register_duplication off -global_opt off -cm area -ir off -pr off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 11 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <ise_file> <fname>.ngd
  • map -intstyle ise -p xc4vlx25-ff668-11 -timing -logic_opt off -ol high -t 1 -register_duplication off -global_opt off -cm area -ir off -pr off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 11 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <ise_file> <fname>.ngd
  • map -intstyle ise -p xc4vlx25-ff668-11 -timing -logic_opt off -ol high -t 1 -register_duplication off -global_opt off -cm area -ir off -pr off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 11 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <ise_file> <fname>.ngd
  • map -intstyle ise -p xc4vlx25-ff668-11 -timing -logic_opt off -ol high -t 1 -register_duplication off -global_opt off -cm area -ir off -pr off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 11 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
_impact 15 15 0 0 0 0 0
arwz 17 17 0 0 0 0 0
bitgen 23 23 0 0 0 0 0
bitinit 18 18 0 0 0 0 0
edif2ngd 19 19 0 0 0 0 0
elfcheck 208 207 0 0 0 0 0
libgen 27 24 0 0 0 0 0
map 20 20 0 0 0 0 0
ngcbuild 33 33 0 0 0 0 0
ngdbuild 21 21 0 0 0 0 0
par 20 20 0 0 0 0 0
platgen 7 5 0 0 0 0 0
psf2Edward 5 5 0 0 0 0 0
trce 19 19 0 0 0 0 0
xawinfo 16 16 0 0 0 0 0
xbash 6 5 0 0 0 0 0
xdsgen 3 3 0 0 0 0 0
xps 69 20 0 0 0 0 0
xst 141 140 0 0 0 0 0
 
Help Statistics
Help files
/doc/usenglish/isehelp/cgn_c_cust_gui_overview.htm ( 1 )
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor PROP_intProjectCreationTimestamp=2011-01-26T08:32:07
PROP_intWbtProjectID=31D7AF4A31F04599B2550A627B666D00 PROP_intWbtProjectIteration=16
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_xilxBitgStart_Clk_MatchCycle=NoWait PROP_xilxMapTimingDrivenPacking=true
PROP_AutoTop=true PROP_DevFamily=Virtex4
PROP_SynthConstraintsFile=changed PROP_DevDevice=xc4vlx25
PROP_DevFamilyPMName=virtex4 PROP_DevPackage=ff668
PROP_Synthesis_Tool=XST (VHDL/Verilog) PROP_DevSpeed=-11
PROP_PreferredLanguage=Verilog FILE_COREGEN=2
FILE_UCF=1 FILE_VERILOG=2
FILE_XAW=3
 
Core Statistics
Core Type=fifo_generator_v5_3
c_common_clock=0 c_data_count_width=12 c_din_width=96 c_dout_rst_val=0
c_dout_width=96 c_enable_rst_sync=1 c_error_injection_type=0 c_full_flags_rst_val=0
c_has_almost_empty=0 c_has_almost_full=0 c_has_data_count=0 c_has_int_clk=0
c_has_overflow=0 c_has_rd_data_count=0 c_has_rst=1 c_has_srst=0
c_has_underflow=0 c_has_valid=0 c_has_wr_ack=0 c_has_wr_data_count=0
c_implementation_type=2 c_memory_type=1 c_msgon_val=1 c_overflow_low=0
c_preload_latency=1 c_preload_regs=0 c_prim_fifo_type=4kx9 c_prog_empty_thresh_assert_val=2
c_prog_empty_thresh_negate_val=3 c_prog_empty_type=0 c_prog_full_thresh_assert_val=4093 c_prog_full_thresh_negate_val=4092
c_prog_full_type=0 c_rd_data_count_width=12 c_rd_depth=4096 c_rd_freq=1
c_rd_pntr_width=12 c_underflow_low=0 c_use_dout_rst=1 c_use_ecc=0
c_use_embedded_reg=0 c_use_fwft_data_count=0 c_valid_low=0 c_wr_ack_low=0
c_wr_data_count_width=12 c_wr_depth=4096 c_wr_freq=1 c_wr_pntr_width=12
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUF=1 NGDBUILD_NUM_BUFG=7 NGDBUILD_NUM_BUFGCTRL=1 NGDBUILD_NUM_DCM_ADV=4
NGDBUILD_NUM_FD=35 NGDBUILD_NUM_FDC=632 NGDBUILD_NUM_FDCE=250 NGDBUILD_NUM_FDE=2
NGDBUILD_NUM_FDP=16 NGDBUILD_NUM_FDPE=16 NGDBUILD_NUM_GND=3 NGDBUILD_NUM_IBUF=24
NGDBUILD_NUM_IBUFDS=50 NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_IBUFGDS=3 NGDBUILD_NUM_IDDR=48
NGDBUILD_NUM_INV=8 NGDBUILD_NUM_IOBUF=8 NGDBUILD_NUM_LUT1=68 NGDBUILD_NUM_LUT2=97
NGDBUILD_NUM_LUT2_D=4 NGDBUILD_NUM_LUT2_L=2 NGDBUILD_NUM_LUT3=566 NGDBUILD_NUM_LUT3_L=2
NGDBUILD_NUM_LUT4=276 NGDBUILD_NUM_LUT4_D=4 NGDBUILD_NUM_MUXCY=143 NGDBUILD_NUM_MUXF5=91
NGDBUILD_NUM_MUXF6=24 NGDBUILD_NUM_OBUF=22 NGDBUILD_NUM_OBUFT=118 NGDBUILD_NUM_RAMB16=44
NGDBUILD_NUM_VCC=3 NGDBUILD_NUM_XORCY=102
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUF=1 NGDBUILD_NUM_BUFG=7 NGDBUILD_NUM_BUFGCTRL=1 NGDBUILD_NUM_DCM_ADV=4
NGDBUILD_NUM_FD=35 NGDBUILD_NUM_FDC=632 NGDBUILD_NUM_FDCE=250 NGDBUILD_NUM_FDE=2
NGDBUILD_NUM_FDP=16 NGDBUILD_NUM_FDPE=16 NGDBUILD_NUM_GND=5 NGDBUILD_NUM_IBUF=59
NGDBUILD_NUM_IBUFDS=50 NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_IBUFGDS=3 NGDBUILD_NUM_IDDR=48
NGDBUILD_NUM_INV=8 NGDBUILD_NUM_LUT1=68 NGDBUILD_NUM_LUT2=97 NGDBUILD_NUM_LUT2_D=4
NGDBUILD_NUM_LUT2_L=2 NGDBUILD_NUM_LUT3=566 NGDBUILD_NUM_LUT3_L=2 NGDBUILD_NUM_LUT4=276
NGDBUILD_NUM_LUT4_D=4 NGDBUILD_NUM_MUXCY=143 NGDBUILD_NUM_MUXF5=91 NGDBUILD_NUM_MUXF6=24
NGDBUILD_NUM_OBUF=22 NGDBUILD_NUM_OBUFT=126 NGDBUILD_NUM_RAMB16=44 NGDBUILD_NUM_TS_TIMESPEC=1
NGDBUILD_NUM_VCC=5 NGDBUILD_NUM_XORCY=102